From chips to systems: How AI is reshaping semiconductor competition

Semiconductor makers have long measured success by what happens inside a single die. That era is ending. The rise of artificial intelligence is forcing a fundamental shift: companies now must optimize performance, cost and reliability across entire systems—spanning packages, racks and supply chains—rather than within isolated components.

This transition pushes critical challenges earlier in the development process. Packaging, connectivity, yield, sourcing and verification, once handled after design was complete, now influence decisions from day one. At the same time, AI is compressing development timelines while multiplying the engineering complexity teams must navigate. Success in the next phase will depend on how effectively organizations coordinate across these interconnected layers.

I think the AI system is our new chips. If we were optimizing everything for the silicon in the past, now these days we're optimizing everything for the system.

Letizia Giuliano, vice president of product management and marketing at Qualcomm Technologies Inc.

These insights emerged from conversations at the GSA Women's Leadership Initiative in Palo Alto, California, where industry leaders discussed AI semiconductor trends with theCUBE Research's John Furrier and co-host Alison Kosik. Topics ranged from optical interconnects and advanced packaging to AI-driven yield learning, physical AI, strategic sourcing and AI-assisted chip design.

1. Connectivity overtakes compute as the bottleneck in AI infrastructure

Data movement between chips, memory and racks now constrains AI performance more than raw processing power, according to Giuliano. At 200 gigabits per second per lane, half the signal budget is consumed simply moving data out of the package. This reality is driving optical interconnect technology from rack-to-rack connections down into racks, blades and packages themselves, with copper and optics working in tandem. Qualcomm recently introduced High Bandwidth Compute, a power-efficient solution for connecting compute to memory optimized around tokens per watt.

Delivering such products at hyperscale volumes requires product engineering to collaborate with design-for-test, manufacturing and reliability teams from the outset, explained Sophie Wang, senior director of product engineering at Marvell Technology Inc.

2. Advanced packaging moves from afterthought to system architecture

The definition of an AI system boundary is shifting from the individual chip to the package itself, emphasized Nisha Ananthakrishnan, senior director of advanced packaging at Intel Corp. Intel leverages its EMIB bridge technology to interconnect chiplets and scale packages across form factors ranging from 3x to more than 10x. Outsourced assembly and test providers are evolving into system integrators, noted Patricia MacLeod, senior director of corporate communications and industry partnerships at Advanced Semiconductor Engineering Inc., pointing to ASE's VIPack platform, which encompasses technologies from fan-out chip-on-substrate to co-packaged optics.

Many components critical to AI systems—including power management chips and voltage regulators manufactured at 12 to 28 nanometers—rely on mature process nodes, added Tazrien Kamal, senior director of technology and innovation at GlobalFoundries Inc.

3. AI-driven yield learning turns speed to volume into a competitive edge

Between 70% and 80% of issues discovered during volume manufacturing scale-up could have been identified before tapeout, highlighted Preeti Prasher, chief operating officer of Stathera Inc. Applying AI to characterization data, simulation results and inline manufacturing information enables teams to begin new wafer runs before defective lots reach testing. Adaptive testing further reduces test duration.

Lattice Semiconductor Corp. has unveiled Lattice Prompt, its inaugural AI design assistant, which converts natural-language specifications into field-programmable gate array designs and identifies the optimal part for a given form factor and budget, according to Iliana Chen, senior director of program management at Lattice. Volume production has emerged as Lattice's primary constraint, driven by demand from robotics and adjacent markets, Chen noted.

4. Physical AI becomes a system-level challenge, not a chip war

Physical AI extends far beyond humanoid robots to encompass any autonomous system that perceives its environment, makes decisions and acts in the physical world, explained Gina Longoria, VP of external communications at Arm Ltd. The sector remains in its infancy, and no single organization can independently establish the architecture, security and safety standards required, she emphasized. Firmware is emerging as the integration layer that unifies GPUs, CPUs, network cards and Compute Express Link devices into cohesive fleet-scale systems, shared Lakshmi Ramagiri, partner for firmware engineering at Microsoft Corp.

Security must evolve beyond secure boot to establish continuous trust during runtime operations, Ramagiri added, identifying the Open Compute Project and DMTF as critical standards bodies to monitor.

5. Strategic sourcing becomes a product decision as AI strains the supply chain

Sourcing has transcended price negotiation to directly influence product development, risk management and customer satisfaction, emphasized Alisa Wang, AVP of global planning and procurement at Credo Technology Group Holding Ltd. Because AI-driven demand can shift dramatically within a single year, suppliers must function as strategic partners with early access to product roadmaps, she noted.

Advanced logic capacity at Taiwan Semiconductor Manufacturing Co. Ltd. represents the tightest constraint, followed by packaging, specialty materials and critical equipment. In response, Credo is qualifying alternative suppliers and expanding its manufacturing footprint across multiple regions. Stathera's Prasher highlighted dual sourcing for critical segments and leveraging supplier input during new product launches to create cost-competitive offerings collaboratively.

6. AI agents compress chip design as development cycles shrink to six to nine months

AI is transitioning from a productivity tool to an embedded component of electronic design automation workflows, explained Rimi Dasgupta, chief of staff for product management and markets at Synopsys Inc., and Vidya Neerkundar, director of product management at Siemens Digital Industries Software. Synopsys has observed verification closure on register-transfer-level designs accelerate by as much as 50-fold and debug duration decrease by 40%, according to Dasgupta.

Rising demand for workload-optimized custom silicon has compressed development timelines from 18 months to six to nine months. Since AI operates probabilistically while chips must be deterministic, Synopsys pairs AI with multiphysics solvers from its Ansys acquisition and is collaborating with OpenAI Group PBC on a dedicated GPT-Synopsys model. Multi-die design represents the next major evolution as chips approach reticle limits, Neerkundar noted.