Celero Lands $275M to Scale Coherent Chips for AI Data Centers

Celero Communications Inc., which specializes in data center networking chips, unveiled a $275 million funding round today. The Series C financing was anchored by Alphabet Inc.'s CapitalG fund, Atreides Management and Valor Equity Partners, with participation from returning investors Sutter Hill Ventures and Maverick Silicon. The round values Celero at $3 billion.

Data centers rely on fiber-optic cables spanning distances exceeding 100 miles to interconnect their facilities. These cables depend on specialized semiconductors known as coherent digital signal processors, or DSPs, to manage the transmission of data across long distances.

The Irvine, California company is engineering a coherent DSP tailored to handle artificial intelligence workloads with reduced latency and lower power consumption compared to existing solutions. Coherent DSPs oversee a data center's transceivers—optical modules that convert digital electrical signals into light for transmission through fiber-optic cables and back into electrical signals upon arrival.

Many applications require knowledge of when network requests originate. Traditionally, this demanded a dedicated physical connection for servers to share timing information, introducing design complexity and expense. Coherent DSPs eliminate this need by extracting timing data without supplementary hardware.

These chips also strengthen network dependability. Signal degradation within fiber-optic cables causes data loss, which coherent DSPs counteract by appending error-correction bits that allow receiving equipment to recover corrupted transmissions.

Celero's coherent DSP addresses both inter-data-center connections and internal network infrastructure. The chip accommodates scale-up networking, which connects processors within a single rack, and scale-out networking, which links separate racks together.

The architecture combines conventional digital transistors with analog circuitry. Digital transistors process discrete signals representing binary values, while analog circuitry handles continuous, time-varying currents. Celero leverages analog components to interface with optical equipment.

A significant achievement preceded today's announcement: Celero validated a chip design manufactured using a two-nanometer process, the most cutting-edge semiconductor fabrication available. Taiwan Semiconductor Manufacturing Co.'s two-nanometer technology delivers 15% performance gains over its predecessor.

Celero's two-nanometer design supports 1.6T and 3.2T interconnects capable of transmitting up to 3.2 terabits per second per port—substantially faster than current AI network infrastructure.

AI infrastructure is rapidly outgrowing the capabilities of traditional optical interconnect architectures. Our two-nanometer silicon validation demonstrates that coherent technology can deliver the bandwidth density, power efficiency and scalability required for the next generation of AI networks.

Nariman Yousefi, Celero co-founder and Chief Executive Officer

Celero intends to deploy the capital toward accelerating product development and advancing its manufacturing timeline.