Marvell's bold chip strategy positions it as AI infrastructure leader

Marvell Technology made an unconventional decision nearly a decade ago that has reshaped its standing in the semiconductor industry. Rather than following the traditional progression of smaller nanometer process nodes, the chipmaker chose to leap ahead, a strategy that has proven prescient as artificial intelligence infrastructure demand accelerates.

In the semiconductor sector, nanometer designations represent generations of manufacturing technology, or process nodes, not literal transistor dimensions. Smaller process nodes typically deliver higher transistor density alongside gains in performance and power consumption. Chipmakers customarily advance through sequential node reductions, making skipped generations an exceptionally risky proposition.

Marvell took that risk. According to Will Chu, executive vice president and general manager of the Custom Cloud Solutions Business Unit at Marvell, "Back around 2018, 2019, we made a decision that if we wanted to do data infrastructure, we needed to be a leader and not a follower, and that meant jumping to the latest process node with the best technology. So, we skipped 7 nanometer. We had products like 12 and 16 nanometer and the next logical one would have been 7. We jumped all the way to 5…we kept going – 3 nanometer, 2 nanometer, 14 angstrom. We've been running that playbook, and it's really served as the foundation for our growth to be a leader in the cloud."

Optical solutions for AI architectures

Marvell has anchored its platform around serializer/deserializer (SerDes) technology, which enables high-speed, multi-gigabit data transmission across AI clusters, cloud data centers and enterprise networks. As data center operators grapple with scaling AI infrastructure, Marvell has deployed SerDes to enhance power efficiency.

The company revealed 2-nanometer optical interconnect technologies in September intended for AI scale-up architectures, which bind multiple computing and memory resources into unified larger systems.

David Lazovsky, executive vice president and general manager of the Data Center Networking Business Group at Marvell, explained the significance: "Why interconnectivity with scale-up moving from copper to optics is so important is because processor-to-processor data transmission, roughly 85% of total data transmission, is happening inside of these scale-up networks, and only 15% across the scale-out network. If you can positively impact the energy efficiency, you can move the needle significantly. We're developing technologies that leverage optics and SerDes … that significantly reduce the total power consumption."

Marvell's emphasis on efficient design has also driven progress in high-bandwidth memory. The company announced a Photonic Fabric Memory Module in August, engineered to establish a shared-memory tier spanning AI infrastructure. This technology merges DDR5 memory, high-bandwidth memory caching and optical connectivity, enabling memory resources to be distributed across AI systems.

According to Lazovsky, "For the first time ever, Marvell has developed optically interconnected high capacity, high bandwidth memory. There are two stacks of high bandwidth memory, and this supports a module with up to eight stacks of Double Data Rate 5. It provides you the ability to decouple memory capacity from compute for the first time."

Marvell's innovations in memory and optical networking have solidified its foothold in the AI infrastructure sector. Nvidia Corp. committed a $2 billion investment in the company earlier this year, and Marvell disclosed an arrangement to engineer custom AI chips for Google LLC.

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Chu characterized the current moment: "This is the biggest buildout in CapEx in human history. In terms of our connectivity business, our networking business, and our custom business, we're attached to the fastest growing part of those markets. We have the leading technology, we have the customer credibility, a track record of execution."